Among conventional semiconductor-memory devices, a non-volatile semiconductor-memory device having cell transistors as shown in FIG. 14 is known as a non-volatile semiconductor-memory device that stores a plurality of bits of information per cell (prior art 1). The non-volatile semiconductor-memory device of prior art 1 comprises: two strip-shaped reverse-conductive areas 123a, 123b that are formed on the top layer of a semiconductor substrate 121, on opposite sides of a strip-shaped conductive semiconductor layer 124a; a first floating gate 127a that is formed via an insulating film 122a such that it extends from the top of one of the reverse-conductive areas 123a over one of the side surfaces of the semiconductor layer 124a; a second floating gate 127b that is formed via an insulating film 122b such that is extends from the top of the other reverse-conductive area 123b over the other side surface of the semiconductor layer 124a; and a control gate 130a that is formed via an insulating film 128 on the top surface of the semiconductor layer 124a (refer to Patent Document 1). With the non-volatile semiconductor-memory device of this prior art 1, reliability of the construction itself is high, and it is possible to maintain localization of a captured charge even when writing a large amount, and to suppress fluctuation in the threshold voltage. Here, miniaturization is possible just by the overlapping portions between the floating gates 127a, 127b and the reverse-conductive areas 123a, 123b. 
Also, among conventional semiconductor-memory devices, a non-volatile semiconductor-memory device as shown in FIG. 15 and FIG. 16 is known (prior art 2). The non-volatile semiconductor-memory device of this prior art 2 comprises: a first diffusion area 207a and a second diffusion area 207b that are arranged in a memory cell on the surface of the substrate so that they are parallel and separated from each other; a selector gate 203 that is located via an insulating film 202 on the substrate 201 in the area between the first and second diffusion areas 207a, 207b; and a third diffusion area (221 in FIG. 15) that is located on the surface of the substrate 201 below the selector gate 203 outside the cell area so that it extends in the direction that crosses the selector gate 203; and having a floating gate 206 that is located via an insulating film 202 in a first area between the first diffusion area 207a and selector gate 203, and in a second area between the second diffusion area 207b and selector gate 203, and a control gate 211 that is located via an insulating film 208 on top of the floating gate 206 and selector gate 203; where the first diffusion area 207a, floating gate 206, control gate 211 and selector gate 203 form a first unit cell, and the second diffusion area 207b, floating gate 206, control gate 211 and selector gate 203 for a second unit cell. In the non-volatile semiconductor-memory device of prior art 2, by applying a positive voltage to the selector gate 203, an inversion layer 220 is formed on the surface of the substrate below the selector gate 203 inside the cell area. The non-volatile semiconductor-memory device of prior art 2 differs from the non-volatile semiconductor-memory device of prior art 1 in that: (1) there is a selector gate 203; (2) an inversion layer 220 is formed below the selector gate 203 inside the cell area when a positive voltage is applied to the selector gate 203; and (3) the area below the floating gate 206 is used as a channel.
The operation of the non-volatile semiconductor-memory device of prior art 2 will be explained using the drawings. FIG. 17 is a drawing for explaining the reading operation (reading operation when no electrons have accumulated in the floating gate) of the semiconductor-memory device of prior art 2. FIG. 18 is a drawing for explaining the writing operation of the semiconductor-memory device of prior art 2. FIG. 19 is a drawing for explaining the erasing operation of the semiconductor-memory device of prior art 2.
Referring to FIG. 17, in the reading operation, in the state in which electrons have not accumulated in the floating gate 206 (erasing state: low threshold voltage), by applying a positive voltage to the control gate 211, selector gate 203 and third diffusion area (221 in FIG. 15), electrons e travel from the second diffusion area 207b along a channel directly below the floating gate 206, and along the inversion layer 220 formed below the selector gate 203 to the third diffusion area (221 in FIG. 15). On the other hand, in the state in which electrons have accumulated in the floating gate 206 (write state: high threshold voltage), there is no channel below the floating gate 206 so no electrons e flow even when a positive voltage is applied to the control gate 211, selector gate 203 and third diffusion area (221 in FIG. 15) (not shown in the figure). Reading is performed by judging data (0/1) according to whether or not electrons e flow.
Referring to FIG. 18, in the writing operation, by applying a high positive voltage to the control gate 211 and second diffusion area 207b, and applying a low positive voltage so that a current of about 1 μA flows in the memory cell of the selector gate 203, electrons e travel from the third diffusion area (211 in FIG. 15) along the inversion layer 220 that is formed below the selector gate 203 to the second diffusion area 207b. When this happens, since part of the electrons e have high energy due to the electric field at the boundary between the selector gate 203 and floating gate 206, they pass through the insulating film 205 (tunnel oxidation film) below the floating gate 206 and infuse into the floating gate 206.
Referring to FIG. 19, in the erasing operation, by applying a high negative voltage to the control gate 211 and applying a high positive voltage to the substrate 201, electrons e are drawn away from the floating gate 206 and pass through the insulating film 205 (tunnel oxidation film) below the floating gate 206 to the substrate 201.
In comparison with the non-volatile semiconductor-memory device of prior art 1, with this non-volatile semiconductor-memory device of prior art 2, construction is such that by performing reading using the selector gate 203 channel as a drain, reading is performed of a target memory node of an independent unit cell, which faces a non-target memory node and is located on the other side of the selector gate 203, without reading the non-target memory node of the other unit cell, and thus essentially functions as a 1-bit cell, so it advantageous in that it is possible to obtain stable circuit operation.
[Patent Document 1] Japanese Patent No. 3,249,811
The entire disclosure thereof being incorporated herein by reference thereto.